The present invention relates to a data processing apparatus and, more particularly, to a technique which is effective when it is used in an interruption control apparatus of a microcomputer.
A central processing unit (CPU) of a microcomputer includes: a data register or an address register called a general register, accumulator, index register, or the like; a program counter; and a control register such as a condition code register or the like as disclosed in, for example, "H8/330, HD6473308, HD6433308, Hardware Manual", Hitachi Ltd., pages 23 to 60 and 71 to 84, published on August, 1989, (corresponding English Version, "H8/300, HD6473308, HD6433308, Hardware Manual", pages 25 to 76, published on December, 1989).
Such a condition code register includes flags which reflect the results of data processes of the CPU: for instance, a zero flag, a negative flag, a carry flag, an overflow flag, and a half carry flag. For example, when the CPU executes the addition, if a carry occurs, the carry flag is set to 1. If no carry occurs, the carry flag is cleared to 0.
The microcomputer has what is called an interrupting function such that when an external factor which is independent of the process of the CPU occurs or when a predetermined operation of a built-in functional block (timer or the like) occurs, the process of the CPU is temporarily interrupted, thereby enabling the process corresponding to the external factor or the operation of the functional block to be executed. When the CPU executes such an interrupting function, the contents in the program counter and condition code register are saved to the outside of the CPU, namely, into what is called a stack area. On the other hand, when the execution of the above interrupting process is finished, a return command is executed and the process of the CPU is returned to the state before execution of the interrupting function. The saved contents of the program counter and the condition code register are recovered.
For instance, the CPU disclosed in the above "H8/330, HD6473308, HD6433308, Hardware Manual", Hitachi Ltd., pages 23 to 60 and 71 to 84, published on August, 1989, includes sixteen general registers each having a 8-bit construction, a 16-bit program counter, and an 8-bit condition code register. In addition to the zero flag, negative flag, and the like, an interruption mask bit and user's bits of two bits are included in the condition code register. When "1" is set into the interruption mask bit, the interruption is inhibited. When the interruption mask bit is cleared to "0", the interruption is permitted. When the interrupting function is executed, the interruption mask bit is set to "1". The condition code register changes due to the reflection of the result of the data process and the execution of the interrupting function as mentioned above. The condition code register can be also operated (set/reset) by a software program through a logical arithmetic operation with immediate data or the like. The 2-bit user's bits are not changed due to the result of the data process or the execution of the interrupting function but can be changed only by a software program. The user's bits are automatically saved upon execution of the interrupting function and is returned by a return command and can be used for management of softwares or the like because of the nature such that it doesn't depend on the result of data process. By using the user's bits, the softwares can be easily managed and the executing efficiency can be improved.
Each of the external factor as an interruption requesting side or a factor of the functional block has a permission bit. A status of the permission bit is set by the CPU and is used to perfectly inhibit the interruption from peripheral circuits such that they are not used on a system or the like. When the permission bit has been cleared to "0", no interruption is requested to the CPU irrespective of the external factor or the operation of the functional block corresponding to the permission bit. When the permission bit has been set to "1", the interruption is requested by the external factor or the predetermined operation of the functional block corresponding to the permission bit. The CPU can inhibit the interruption by the interruption mask bit. Namely, even when the interruption is requested, so long as the interruption mask bit has been set to "1", such an interruption request is reserved until the interruption mask bit is cleared to "0". When the interruption is requested, so long as the interruption mask bit has been cleared to "0", such an interruption request is accepted to the CPU at a time point of the end of the command which is being executed. The interrupting process is executed.